SH7147 Datasheet, PDF (550/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 12 Watchdog Timer (WDT)
12.5 Usage Note
12.5.1 WTCNT Setting Value
If WTCNT is set to H'FF in interval timer mode, overflow does not occur when WTCNT changes
from H'FF to H'00 after one cycle of count clock, but overflow occurs when WTCNT changes
from H'FF to H'00 after 257 cycles of count clock.
If WTCNT is set to H'FF in watchdog timer mode, overflow occurs when WTCNT changes from
H'FF to H'00 after one cycle of count clock.
Rev. 3.00 Oct. 06, 2008 Page 526 of 1080
REJ09B0230-0300