SH7147 Datasheet, PDF (76/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 3 MCU Operating Modes
3.4 Address Map
The address maps for the operating modes are shown in figures 3.1 to 3.4.
H'00000000
Mode 0
On-chip ROM disabled mode
Mode 2
On-chip ROM enabled mode
H'00000000
H'00000000
Mode 3
Single chip mode
On-chip ROM (256 Kbytes)
On-chip ROM (256 Kbytes)
CS0 space
H'03FFFFFF
H'04000000
H'0003FFFF
H'00040000
H'01FFFFFF
H'02000000
H'03FFFFFF
H'04000000
Reserved area
CS0 space
H'0003FFFF
H'00040000
CS1 space
H'07FFFFFF
H'08000000
CS1 space
H'07FFFFFF
H'08000000
Reserved area
Reserved area
Reserved area
H'FFFF8FFF
H'FFFF9000
H'FFFF8FFF
H'FFFF9000
H'FFFF8FFF
H'FFFF9000
On-chip RAM (12 Kbytes)
On-chip RAM (12 Kbytes)
On-chip RAM (12 Kbytes)
H'FFFFBFFF
H'FFFFC000
H'FFFFFFFF
On-chip peripheral
I/O registers
H'FFFFBFFF
H'FFFFC000
H'FFFFFFFF
On-chip peripheral
I/O registers
H'FFFFBFFF
H'FFFFC000
H'FFFFFFFF
On-chip peripheral
I/O registers
Figure 3.1 Address Map for Each Operating Mode
(256-Kbyte On-Chip ROM/12-Kbyte On-Chip RAM Version)
Rev. 3.00 Oct. 06, 2008 Page 52 of 1080
REJ09B0230-0300