SH7147 Datasheet, PDF (1005/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 24 List of Registers
Register Name
Abbreviation
Common control register
CMNCR
CS0 space bus control register CS0BCR
CS1 space bus control register CS1BCR
CS0 space wait control register CS0WCR
CS1 space wait control register CS1WCR
RAM emulation register
RAMER
No. of
Bits Address
Module
32
H'FFFFF000 BSC
32
H'FFFFF004
32
H'FFFFF008
32
H'FFFFF028
32
H'FFFFF02C
16
H'FFFFF108 FLASH
Break address register A
BARA
32
H'FFFFF300 UBC
Break address mask register A BAMRA
32
H'FFFFF304
Break bus cycle register A
BBRA
16
H'FFFFF308
Break data register A
BDRA
32
H'FFFFF310
Break data mask register A
BDMRA
32
H'FFFFF314
Break address register B
BARB
32
H'FFFFF320
Break address mask register B BAMRB
32
H'FFFFF324
Break bus cycle register B
BBRB
16
H'FFFFF328
Break data register B
BDRB
32
H'FFFFF330
Break data mask register B
BDMRB
32
H'FFFFF334
Break control register
BRCR
32
H'FFFFF3C0 UBC
Branch source register
BRSR
32
H'FFFFF3D0
Branch destination register
BRDR
32
H'FFFFF3D4
Execution times break register BETR
16
H'FFFFF3DC
AUD control register
AUCSR
32
H'FFFFF400 AUD
AUD window A start address
register
AUWASR
32
H'FFFFF404
AUD window A end address
register
AUWAER
32
H'FFFFF408
AUD window B start address
register
AUWBSR
32
H'FFFFF40C
AUD window B end address
register
AUWBER
32
H'FFFFF410
AUD extended control register AUECSR
32
H'FFFFF414
Notes: 1. Available only in the SH7142.
2. At read operation.
3. At write operation.
Access Size No. of Access Cycles
Connected
Bus Width
32
Bφ (reference clock)
16 bits
32
L: 2
32
32
32
16
Bφ (reference clock)
16 bits
W: 2
32
Bφ (reference clock)
16 bits
32
B: 2
16
W: 2
32
L: 2
32
32
32
16
32
32
32
Iφ (reference clock)
16 bits
32
B: 2
32
W: 2
16
L: 2
32
Bφ (reference clock)
16 bits
32
L: 2
32
32
32
32
Rev. 3.00 Oct. 06, 2008 Page 981 of 1080
REJ09B0230-0300