SH7147 Datasheet, PDF (536/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 11 Port Output Enable (POE)
11.4.1 Input Level Detection Operation
If the input conditions set by ICSR1 to ICSR3 occur on the POE0 to POE2, POE4 to POE6, and
POE8 pins, the special pins of the MTU2 and MTU2S and the pins for channel 0 of the MTU2 are
placed in the high-impedance state. Note however, that these special pins and MTU2 pins enter
high-impedance state only when general input/output function, MTU2 function, or MTU2S
function is selected for these pins.
(1) Falling Edge Detection
When a change from a high to low level is input to the POE0 to POE2, POE4 to POE6, and POE8
pins, the special pins of the MTU2 and MTU2S and the pins for channel 0 of the MTU2 are placed
in the high-impedance state. Figure 11.2 shows a sample timing after the level changes in input to
the POE0 to POE2, POE4 to POE6, and POE8 pins until the respective pins enter high-impedance
state.
Pφ
POE input
Pφ rising edge
Falling edge detection
PE9/TIOC3B
High-impedance state*
Note: * Other special pins of MTU2 and MTU2S also enter the high-impedance state with the same timing.
Figure 11.2 Falling Edge Detection
Rev. 3.00 Oct. 06, 2008 Page 512 of 1080
REJ09B0230-0300