SH7147 Datasheet, PDF (13/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

10.3.18 Timer Read/Write Enable Register (TRWER).................................................. 311
10.3.19 Timer Output Master Enable Register (TOER) ................................................ 312
10.3.20 Timer Output Control Register 1 (TOCR1) ...................................................... 313
10.3.21 Timer Output Control Register 2 (TOCR2) ...................................................... 316
10.3.22 Timer Output Level Buffer Register (TOLBR) ................................................ 319
10.3.23 Timer Gate Control Register (TGCR)............................................................... 320
10.3.24 Timer Subcounter (TCNTS) ............................................................................. 322
10.3.25 Timer Dead Time Data Register (TDDR)......................................................... 323
10.3.26 Timer Cycle Data Register (TCDR) ................................................................. 323
10.3.27 Timer Cycle Buffer Register (TCBR)............................................................... 324
10.3.28 Timer Interrupt Skipping Set Register (TITCR) ............................................... 324
10.3.29 Timer Interrupt Skipping Counter (TITCNT)................................................... 326
10.3.30 Timer Buffer Transfer Set Register (TBTER) .................................................. 327
10.3.31 Timer Dead Time Enable Register (TDER)...................................................... 329
10.3.32 Timer Waveform Control Register (TWCR) .................................................... 330
10.3.33 Bus Master Interface ......................................................................................... 332
10.4 Operation .......................................................................................................................... 333
10.4.1 Basic Functions................................................................................................. 333
10.4.2 Synchronous Operation..................................................................................... 339
10.4.3 Buffer Operation ............................................................................................... 341
10.4.4 Cascaded Operation .......................................................................................... 345
10.4.5 PWM Modes ..................................................................................................... 350
10.4.6 Phase Counting Mode ....................................................................................... 355
10.4.7 Reset-Synchronized PWM Mode...................................................................... 362
10.4.8 Complementary PWM Mode ............................................................................ 365
10.4.9 A/D Converter Start Request Delaying Function.............................................. 409
10.4.10 MTU2–MTU2S Synchronous Operation.......................................................... 413
10.4.11 External Pulse Width Measurement.................................................................. 419
10.4.12 Dead Time Compensation................................................................................. 420
10.4.13 TCNT Capture at Crest and/or Trough in Complementary PWM Operation ... 422
10.5 Interrupt Sources............................................................................................................... 423
10.5.1 Interrupt Sources and Priorities......................................................................... 423
10.5.2 DTC Activation................................................................................................. 425
10.5.3 A/D Converter Activation................................................................................. 426
10.6 Operation Timing.............................................................................................................. 428
10.6.1 Input/Output Timing ......................................................................................... 428
10.6.2 Interrupt Signal Timing..................................................................................... 435
10.7 Usage Notes ...................................................................................................................... 440
10.7.1 Module Standby Mode Setting ......................................................................... 440
10.7.2 Input Clock Restrictions ................................................................................... 440
Rev. 3.00 Oct. 06, 2008 Page xiii of xxiv
REJ09B0230-0300