SH7147 Datasheet, PDF (178/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 7 User Break Controller (UBC)
7.5 Usage Notes
1. The CPU can read from or write to the UBC registers via the I bus. Accordingly, during the
period from executing an instruction to rewrite the UBC register till the new value is actually
rewritten, the desired user break may not occur. In order to know the timing when the UBC
register is changed, read from the last written register. Instructions after then are valid for the
newly written register value.
2. UBC cannot monitor access to the L bus and I bus in the same channel.
3. Note on specification of sequential break:
A condition match occurs when a B-channel match occurs in a bus cycle after an A-channel
match occurs in another bus cycle in sequential break setting. Therefore, no user break occurs
if a bus cycle in which an A-channel match and a channel B match occur simultaneously is set.
4. When a user break and another exception occur at the same instruction, which has higher
priority is determined according to the priority levels defined in table 5.1. If an exception with
higher priority occurs, the user break is not generated.
⎯ Pre-execution break has the highest priority.
⎯ When a post-execution break or data access break occurs simultaneously with a re-
execution-type exception (including pre-execution break) that has higher priority, the re-
execution-type exception is accepted, and the condition match flag is not set (see the
exception in the following note). The user break will occur and the condition match flag
will be set only after the exception source of the re-execution-type exception has been
cleared by the exception handling routine and re-execution of the same instruction has
ended.
⎯ When a post-execution break or data access break occurs simultaneously with a
completion-type exception (TRAPA) that has higher priority, a user break does not occur
but the condition match flag is set.
5. Note the following exception for the above note.
If a post-execution break or data access break is satisfied by an instruction that generates a
CPU address error by data access, the CPU address error takes priority over the user break.
Note that the UBC condition match flag is set in this case.
6. Note the following when a user break occurs in a delay slot.
If a pre-execution break is set at the delay slot instruction of the RTE instruction, the user
break does not occur until the branch destination of the RTE instruction.
Rev. 3.00 Oct. 06, 2008 Page 154 of 1080
REJ09B0230-0300