SH7147 Datasheet, PDF(211/1108 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

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SH7147 Datasheet, PDF (211/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

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Section 8 Data Transfer Controller (DTC)

Clock (BÏ)

DTC activation

request

DTC request

Internal address

R

W

RW

Vector read

Transfer information

read

Data Transfer information Transfer information

transfer

write

read

Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined.

Data Transfer information

transfer

write

Figure 8.12 Example of DTC Operation Timing: Chain Transfer

(Activated by On-Chip Peripheral Module; IÏ : BÏ : PÏ = 1 : 1/2 : 1/2;

Data Transferred from On-Chip Peripheral Module to On-Chip RAM;

Transfer Information is Written in 3 Cycles)

8.5.8 Number of DTC Execution Cycles

Table 8.9 shows the execution status for a single DTC data transfer, and table 8.10 shows the

number of cycles required for each execution.

Table 8.9 DTC Execution Status

Mode

Vector

Read

I

Transfer

Information

Read

J

Transfer

Information

Write

K

Normal 1

0*1 4

0*1

3

2*2 1*3

Repeat 1

0*1 4

0*1

3

2*2 1*3

Block

1

transfer

0*1 4

0*1

3

2*2 1*3

[Legend]

P: Block size (CRAH and CRAL value)

Notes: 1. When transfer information read is skipped

2. When the SAR or DAR is in fixed mode

3. When the SAR and DAR are in fixed mode

Data Read

L

Data

Write

M

1

1

1

1

1â¢P

1â¢P

Internal

Operation

N

1

0*1

1

0*1

1

0*1

Rev. 3.00 Oct. 06, 2008 Page 187 of 1080

REJ09B0230-0300

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