SH7147 Datasheet, PDF (214/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Data Transfer Controller (DTC)
Clock (Bφ)
DTC activation
request 1
DTC activation
request 2
DTC request
Bus release timing
DTLOCK = 1
Bus release timing
DTLOCK = 0
Internal address
RW
RW
Vector
read
Transfer information Data Transfer information Vector
read
transfer
write
read
Transfer information Data Transfer information
read
transfer
write
[Legend]
: Indicates bus mastership release timing.
: Indicates bus mastership release timing that may occur depending on the CPU execution status.
: Bus mastership is only released for the external access request from the CPU after a vector read.
Note: DTC request signal indicates the state of internal bus request after the DTC activation source is determined.
Figure 8.13 Example of DTC Operation Timing:
Conflict of Two Activation Requests in Normal Transfer Mode
(Activated by On-Chip Peripheral Module; Iφ : Bφ : Pφ = 1 : 1/2 : 1/2;
Data Transferred from On-Chip Peripheral Module to On-Chip RAM;
Transfer Information is Written in 3 Cycles)
Rev. 3.00 Oct. 06, 2008 Page 190 of 1080
REJ09B0230-0300