SH7147 Datasheet, PDF (163/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 7 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W Description
10
PCBA
0
R/W PC Break Select A
Selects the break timing of the instruction fetch cycle
for channel A as before or after instruction execution.
0: PC break of channel A is set before instruction
execution
1: PC break of channel A is set after instruction
execution
9, 8
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
7
DBEA
0
R/W Data Break Enable A
Selects whether or not the data bus value is included
in the channel A break condition.
0: The data bus value is not included in the channel A
break condition
1: The data bus value is included in the channel A
break condition
6
PCBB
0
R/W PC Break Select B
Selects the break timing of the instruction fetch cycle
for channel B as before or after instruction execution.
0: PC break of channel B is set before instruction
execution
1: PC break of channel B is set after instruction
execution
5
DBEB
0
R/W Data Break Enable B
Selects whether or not the data bus value is included
in the channel B break condition.
0: The data bus value is not included in the channel B
break condition
1: The data bus value is included in the channel B
break condition
4
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 3.00 Oct. 06, 2008 Page 139 of 1080
REJ09B0230-0300