SH7147 Datasheet, PDF (535/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 11 Port Output Enable (POE)
11.4 Operation
Table 11.4 shows the target pins for high-impedance control and conditions to place the pins in the
high-impedance state.
Table 11.4 Target Pins and Conditions for High-Impedance Control
Pins
MTU2 special pins
(PE9/TIOC3B and
PE11/TIOC3D)
MTU2 special pins
(PE12/TIOC4A and
PE14/TIOC4C)
MTU2 special pins
(PE13/TIOC4B and
PE15/TIOC4D)
MTU2S special pins
(PE16/TIOC3BS and
PE17/TIOC3DS)
MTU2S special pins
(PE18/TIOC4AS and
PE20/TIOC4CS)
MTU2S special pins
(PE19/TIOC4BS and
PE21/TIOC4DS)
MTU2 channel 0 pin
(PE0/TIOC0A)
MTU2 channel 0 pin
(PE1/TIOC0B)
MTU2 channel 0 pin
(PE2/TIOC0C)
MTU2 channel 0 pin
(PE3/TIOC0D)
Conditions
Input level detection,
output level comparison, or
SPOER setting
Input level detection,
output level comparison, or
SPOER setting
Input level detection,
output level comparison, or
SPOER setting
Input level detection,
output level comparison, or
SPOER setting
Input level detection,
output level comparison, or
SPOER setting
Input level detection,
output level comparison, or
SPOER setting
Input level detection or
SPOER setting
Input level detection or
SPOER setting
Input level detection or
SPOER setting
Input level detection or
SPOER setting
Detailed Conditions
MTU2P1CZE •
((POE2F + POE1F + POE0F) +
(OSF1 • OCE1) + (MTU2CH34HIZ))
MTU2P2CZE •
((POE2F + POE1F + POE0F) +
(OSF1 • OCE1) + (MTU2CH34HIZ))
MTU2P3CZE •
((POE2F + POE1F + POE0F) + (OSF1 •
OCE1) + (MTU2CH34HIZ))
MTU2SP1CZE •
((POE4F + POE5F + POE6F) +
(OSF2 • OCE2) + (MTU2SHIZ))
MTU2SP2CZE •
((POE4F + POE5F + POE6F) +
(OSF2 • OCE2) + (MTU2SHIZ))
MTU2SP3CZE •
((POE4F + POE5F + POE6F) +
(OSF2 • OCE2) + (MTU2SHIZ))
MTU2PE0ZE
((POE8F • POE8E) + (MTU2CH0HIZ))
MTU2PE1ZE
((POE8F • POE8E) + (MTU2CH0HIZ))
MTU2PE2ZE
((POE8F • POE8E) + (MTU2CH0HIZ))
MTU2PE3ZE
((POE8F • POE8E) + (MTU2CH0HIZ))
Rev. 3.00 Oct. 06, 2008 Page 511 of 1080
REJ09B0230-0300