SH7147 Datasheet, PDF (521/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 11 Port Output Enable (POE)
Initial
Bit
Bit Name value R/W Description
14 to ⎯
10
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
9
OCE1
0
R/W*² Output Short High-Impedance Enable 1
This bit specifies whether to place the pins in the high-
impedance state when the OSF1 bit in OCSR1 is set to 1.
0: Does not place the pins in the high-impedance state
1: Places the pins in the high-impedance state
8
OIE1
0
R/W Output Short Interrupt Enable 1
This bit enables or disables interrupt requests when the
OSF1 bit in OCSR is set to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
7 to 0 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. Can be modified only once after a power-on reset.
Rev. 3.00 Oct. 06, 2008 Page 497 of 1080
REJ09B0230-0300