SH7147 Datasheet, PDF (702/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 17 Controller Area Network (RCAN-ET)
17.3 Programming Model - Overview
The purpose of this programming interface is to allow convenient, effective access to the CAN bus
for efficient message transfer. Please bear in mind that the user manual reports all settings allowed
by the RCAN-ET IP. Different use of RCAN-ET is not allowed.
17.3.1 Memory Map
The diagram of the memory map is shown below.
H'000
H'002
H'004
H'006
H'008
H'00A
H'00C
Bit 15
Bit 0
Master Control Register (MCR)
General Status Register(GSR)
Bit Configuration Register 1 (BCR1)
Bit Configuration Register 0 (BCR0)
Interrupt Request Register (IRR)
Interrupt Mask Register (IMR)
Transmit Error Counter Receive Error Counter
(TEC)
(REC)
H'020
H'022
Transmit Pending Register (TXPR1)
Transmit Pending Register (TXPR0)
H'02A
Transmit Cancel Register (TXCR0)
H'032
Transmit Acknowledge Register (TXACK0)
H'03A
Abort Acknowledge Register (ABACK0)
H'042
Receive Pending Register (RXPR0)
H'04A
Remote Frame Pending Register (RFPR0)
H'052
Mailbox Interrupt Mask Register (MBIMR0)
H'05A
Unread Message Status Register (UMSR0)
Bit 15
H'0A0
H'0A4
Bit 0
H'100
H'104
H'108
H'10A
H'10C
H'10E
H'110
Mailbox-0 Control 0
(STDID, EXTID, RTR, IDE)
LAFM
0
1
2
3
Mailbox 0 Data (8 bytes)
4
5
6
7
Mailbox-0 Control 1 (NMC, MBC, DLC)
H'120
H'140
H'160
Mailbox-1 Control/LAFM/Data etc.
Mailbox-2 Control/LAFM/Data etc.
Mailbox-3 Control/LAFM/Data etc.
H'2E0
Mailbox-15 Control/LAFM/Data etc.
Figure 17.2 RCAN-ET Memory Map
The locations not used (between H'000 and H'2F2) are reserved and cannot be accessed.
Rev. 3.00 Oct. 06, 2008 Page 678 of 1080
REJ09B0230-0300