SH7147 Datasheet, PDF (516/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 11 Port Output Enable (POE)
11.3 Register Descriptions
The POE has the following registers. For details on register addresses and register states during
each processing, refer to section 24, List of Registers.
Table 11.3 Register Configuration
Register Name
Input level control/status
register 1
Output level control/status
register 1
Input level control/status
register 2
Output level control/status
register 2
Input level control/status
register 3
Software port output enable
register
Port output enable control
register 1
Port output enable control
register 2
Abbrevia-
tion
R/W Initial Value Address
Access Size
ICSR1
R/W H'0000
H'FFFFD000 8, 16, 32
OCSR1
R/W H'0000
H'FFFFD002 8, 16
ICSR2
R/W H'0000
H'FFFFD004 8, 16, 32
OCSR2
R/W H'0000
H'FFFFD006 8, 16
ICSR3
R/W H'0000
H'FFFFD008 8, 16
SPOER
R/W H'00
H'FFFFD00A 8
POECR1 R/W H'00
H'FFFFD00B 8
POECR2 R/W H'7700
H'FFFFD00C 8, 16
Rev. 3.00 Oct. 06, 2008 Page 492 of 1080
REJ09B0230-0300