SH7147 Datasheet, PDF (623/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 14 Synchronous Serial Communication Unit
14.3.2 SS Control Register L (SSCRL)
SSCRL selects operating mode, software reset, and transmit/receive data length.
Bit: 7
6
5
4
3
2
1
0
FCLRM SSUMS SRES -
-
-
DATS[1:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R
R
R R/W R/W
Initial
Bit
Bit Name Value R/W
7
FCLRM 0
R/W
6
SSUMS 0
R/W
5
SRES
0
R/W
4 to 2 ⎯
All 0
R
Description
Flag Clear Mode
Selects whether the SSRXI and SSTXI interrupt flags
are cleared on writing to SSTDR or reading from
SSRDR or on completion of DTC transfer. When using
the DTC, set this bit to 0.
0: Flags are cleared when DTC transfer is completed
1: Flags are cleared when the register is accessed
Selects transfer mode from synchronous serial
communication mode and clock synchronous mode.
0: Synchronous serial communication mode
1: Clock synchronous mode
Software Reset
Setting this bit to 1 forcibly resets the synchronous
serial communication unit internal sequencer. After that,
this bit is automatically cleared. The ORER, TEND,
TDRE, RDRF, and CE bits in SSSR and the TE and RE
bits in SSER are also initialized. Values of other bits for
synchronous serial communication unit registers are
held.
To stop transfer, set this bit to 1 to reset the
synchronous serial communication unit internal
sequencer.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Oct. 06, 2008 Page 599 of 1080
REJ09B0230-0300