SH7147 Datasheet, PDF (226/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
9.3 Area Overview
9.3.1 Area Division
In the architecture, this LSI has 32-bit address spaces.
As listed in tables 9.2 to 9.5, this LSI can connect two areas to each type of memory, and it
outputs chip select signals (CS0 and CS1) for each of them. CS0 is asserted during area 0 access.
9.3.2 Address Map
The external address space has a capacity of 128 Mbytes and is used by dividing into two spaces.
The memory to be connected and the data bus width are specified in each space. The address map
for the entire address space is listed in tables 9.2 to 9.5.
Table 9.2 (1) Address Map (256-Kbyte On-Chip ROM/12-Kbyte On-Chip RAM,
On-Chip ROM-Enabled Mode)
Address
Area
Memory Type
Capacity
Bus
Width
H'00000000 to On-chip ROM
H'0003FFFF
256 Kbytes 32 bits
H'00040000 to Reserved
H'01FFFFFF
H'02000000 to CS0 space
H'03FFFFFF
Normal space
32 Mbytes 8 bits
H'04000000 to CS1 space
H'07FFFFFF
Normal space
64 Mbytes 8 bits
H'08000000 to Reserved
H'FFFF8FFF
H'FFFF9000 to On-chip RAM
H'FFFFBFFF
12 Kbytes 32 bits
H'FFFFC000 to On-chip peripheral
H'FFFFFFFF ^modules
16 Kbytes
8 or 16
bits
Note: Do not access the reserved area. If the reserved area is accessed, the correct operation
cannot be guaranteed. In single-chip mode, only the on-chip ROM, on-chip RAM, and on-
chip peripheral modules can be accessed; the other areas cannot be accessed.
Rev. 3.00 Oct. 06, 2008 Page 202 of 1080
REJ09B0230-0300