SH7147 Datasheet, PDF (730/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 17 Controller Area Network (RCAN-ET)
• TEC/REC (Address = H'00C)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: * It is only possible to write the value in test mode when TST[2:0] in MCR is 3'b100.
REC is incremented during Bus Off to count the recurrences of 11 recessive bits as
requested by the Bus Off recovery sequence.
17.3.4 RCAN-ET Mailbox Registers
The following sections describe RCAN-ET Mailbox registers that control / flag individual
Mailboxes. The address is mapped as follows.
Important : LongWord access is carried out as two consecutive Word accesses.
Rev. 3.00 Oct. 06, 2008 Page 706 of 1080
REJ09B0230-0300