SH7147 Datasheet, PDF (1094/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Main Revisions for This Edition
Item
17.3.4 RCAN-ET Mailbox
Registers
(8) Unread Message Status
Register (UMSR)
17.4.4 Message Receive
Sequence
Figure 17.12 Message
Receive Sequence
Page Revision (See Manual for Details)
715 Note added
726
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
UMSR0[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note : * Only when writing a ‘1’ to clear.
Figure amended
CAN Bus
RCAN-ET
End Of Arbitration Field
IDLE
End Of Frame
Valid CAN-ID Received
Loop (N = 15; N ≥ 0; N = N - 1)
N=N-1
Valid CAN Frame Received
Compare ID with
Mailbox[N] + LAFM[N]
(if MBC is config to receive)
Yes
No
No
ID Matched?
Yes
N = 0?
Yes
Store Mailbox-Number[N]
and go back to idle state
OverWrite
RXPR[N]
(RFPR[N])
Already Set?
No
Yes
MSG
OverWrite or
OverRun?
(NMC)
•Store Message by Overwriting
•Set UMSR
•Set IRR9 (if MBIMR[N] = 0)
•Generate Interrupt Signal
(if IMR9 = 0)
•Set RXPR[N] (RFPR[N])
•Set IRR1 (IRR2) (if MBIMR[N] = 0)
•Generate Interrupt Signal
(if IMR1 (IMR2) = 0)
Interrupt signal
OverRun
•Reject Message
•Set UMSR
•Set IRR9 (if MBIMR[N] = 0)
•Generate Interrupt Signal
(if IMR9 = 0)
•Set RXPR[N] (RFPR[N]) *¹
Interrupt signal
•Store Message
•Set RXPR[N] (RFPR[N])
•Set IRR1 (IRR2) (if MBIMR[N] = 0)
•Generate Interrupt Signal
(if IMR1 (IMR2) = 0)
Interrupt signal
Exit Interrupt Service
Routine
Check and clear
UMSR[N] *²
Check and clear
UMSR[N] *²
Write 1 to RXPR[N] Write 1 to RFPR[N]
Read Mailbox[N]
Read Mailbox[N]
Read RXPR[N] = 1
Read RFPR[N] = 1
Yes
IRR[1]
No
set?
Read IRR
18.1.8 Port E Control Registers 768
L1 to L4, H1, H2 (PECRL1 to
PECRL4, PECRH1, PECRH2)
• Port E Control Register H2
(PECRH2)
20.4.1 Registers
810
Table 20.5 Register/Parameter
and Target Mode
CPU received interrupt due to CAN Message Reception
Notes: 1. Only if CPU clears RXPR[N]/RFPR[N] at the same time that UMSR is set in overrun, RXPR[N]/RFPR[N] may be set again even though the
message has not been updated.
2. In case overwrite configuration (NMC = 1) is used for the Mailbox N the message must be discarded when UMSR[N] = 1, UMSR[N] cleared
and the full Interrupt Service Routine started again. In case of overrun configuration (NMC = 0) is used clear again RXPR[N]/RFPR[N]/
UMSR[N] when UMSR[N] = 1 and consider the message obsolate.
Description amended
Initial
Bit
Bit Name Value R/W
1
PE20MD1 0
R/W
0
PE20MD0 0
R/W
Description
PE20 Mode
Select the function of the PE20/TIOC4CS pin.
00: PE20 I/O (port)
01: TIOC4CS I/O (MTU2S)
Other than above: Setting prohibited
Table amended
Programming/ FCCS
erasing interface _FPCS
registers
FECS
FKEY
FMATS
FTDAR
Initiali-
Download zation
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Program-
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Erasure Read
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*¹
*¹
*²
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RAM
Emulation
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Rev. 3.00 Oct. 06, 2008 Page 1070 of 1080
REJ09B0230-0300