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SH7147 Datasheet, PDF (69/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family | |||
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Section 2 CPU
Instruction
Operation
Code
Execution
Cycles
T Bit
STS MACH,Rn
MACH â Rn
0000nnnn00001010 1
â¯
STS MACL,Rn
MACL â Rn
0000nnnn00011010 1
â¯
STS PR,Rn
PR â Rn
0000nnnn00101010 1
â¯
STS.L MACH,@âRn
Rnâ4 â Rn, MACH â (Rn) 0100nnnn00000010 1
â¯
STS.L MACL,@âRn
Rnâ4 â Rn, MACL â (Rn) 0100nnnn00010010 1
â¯
STS.L PR,@âRn
Rnâ4 â Rn, PR â (Rn) 0100nnnn00100010 1
â¯
TRAPA #imm
PC/SR â Stack area,
11000011iiiiiiii 8
â¯
(imm à 4 + VBR) â PC
Note:
* Number of execution cycles until this LSI enters sleep mode.
About the number of execution cycles:
The table lists the minimum number of execution cycles. In practice, the number of
execution cycles will be increased depending on the conditions such as:
⢠When there is a conflict between instruction fetch and data access
⢠When the destination register of a load instruction (memory â register) is also used
by the instruction immediately after the load instruction.
Rev. 3.00 Oct. 06, 2008 Page 45 of 1080
REJ09B0230-0300
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