SH7147 Datasheet, PDF (261/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) and Multi-Function Timer Pulse Unit 2S (MTU2S)
Table 10.1 MTU2 Functions
Item
Channel 0
Count clock
MPφ/1
MPφ/4
MPφ/16
MPφ/64
TCLKA
TCLKB
TCLKC
TCLKD
General registers
TGRA_0
TGRB_0
TGRE_0
General registers/
buffer registers
TGRC_0
TGRD_0
TGRF_0
I/O pins
TIOC0A
TIOC0B
TIOC0C
TIOC0D
Counter clear
function
TGR compare
match or input
capture
Compare 0 output √
match
output
1 output √
Toggle √
output
Input capture
√
function
Synchronous
√
operation
PWM mode 1
√
PWM mode 2
√
Complementary —
PWM mode
Reset PWM mode —
AC synchronous √
motor drive mode
Channel 1
MPφ/1
MPφ/4
MPφ/16
MPφ/64
MPφ/256
TCLKA
TCLKB
TGRA_1
TGRB_1
—
TIOC1A
TIOC1B
TGR compare
match or input
capture
√
√
√
√
√
√
√
—
—
—
Channel 2
MPφ/1
MPφ/4
MPφ/16
MPφ/64
MPφ/1024
TCLKA
TCLKB
TCLKC
TGRA_2
TGRB_2
—
TIOC2A
TIOC2B
TGR compare
match or input
capture
√
√
√
√
√
√
√
—
—
—
Channel 3
MPφ/1
MPφ/4
MPφ/16
MPφ/64
MPφ/256
MPφ/1024
TCLKA
TCLKB
TGRA_3
TGRB_3
TGRC_3
TGRD_3
TIOC3A
TIOC3B
TIOC3C
TIOC3D
TGR compare
match or input
capture
√
√
√
√
√
√
—
√
√
√
Channel 4
MPφ/1
MPφ/4
MPφ/16
MPφ/64
MPφ/256
MPφ/1024
TCLKA
TCLKB
TGRA_4
TGRB_4
TGRC_4
TGRD_4
TIOC4A
TIOC4B
TIOC4C
TIOC4D
TGR compare
match or input
capture
√
√
√
√
√
√
—
√
√
√
Rev. 3.00 Oct. 06, 2008 Page 237 of 1080
REJ09B0230-0300