SH7147 Datasheet, PDF (881/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 20 Flash Memory
The FLER bit is set to 1 in the following conditions:
1. When the relevant bank area of flash memory is read during programming/erasing (including a
vector read or an instruction fetch)
2. When a SLEEP instruction (including software standby mode) is executed during
programming/erasing
Error protection is cancelled (FLER bit is cleared) only by a power-on reset or in hardware
standby mode.
Note that the reset signal should only be released after providing a reset input over a period longer
than the normal 100 μs. Since high voltages are applied during programming/erasing of the flash
memory, some voltage may still remain even after the error protection state has been entered. For
this reason, it is necessary to reduce the risk of damage to the flash memory by extending the reset
period so that the charge is released.
The state-transition diagram in figure 20.16 shows transitions to and from the error protection
state.
Program mode
Erase mode
RES = 0 or HSTBY = 0
Reset or standby
(Hardware protection)
Read disabled
Programming/erasing
enabled
FLER = 0
Error occurred
Read enabled
Er(rSorofotwccaurerresdtand_{RbEy)SH=S0TBorY}
=
Programming/erasing disabled
FLER = 0
0
Programming/erasing interface
RES = 0 or
register is in its initial state.
HSTBY = 0
Error protection mode Software standby mode
Error protection mode
(Software standby)
Read enabled
Programming/erasing disabled
FLER = 1
Cancel
software standby
mode
Read disabled
Programming/erasing disabled
FLER = 1
Programming/erasing interface
register is in its initial state.
Figure 20.16 Transitions to and from Error Protection State
Rev. 3.00 Oct. 06, 2008 Page 857 of 1080
REJ09B0230-0300