SH7147 Datasheet, PDF (192/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Data Transfer Controller (DTC)
Initial
Bit
Bit Name Value R/W Description
0
ERR
0
R/(W)* Transfer Stop Flag
Indicates that a DTC address error or NMI interrupt has
occurred.
If a DTC address error or NMI interrupt occurs while the
DTC is active, a DTC address error handling or NMI
interrupt handling processing is executed after the DTC
has released the bus mastership. The DTC transfers data
and stops in the transfer information writing state.
0: No interrupt has occurred
1: An interrupt has occurred
[Clearing condition]
• When writing 0 after reading 1
Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
8.2.9 DTC Vector Base Register (DTCVBR)
DTCVBR is a 32-bit register that specifies the base address for vector table address calculation.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W Description
31 to 12
11 to 0 ⎯
All 0
R/W Bits 11 to 0 are always read as 0. The write value should
All 0
R
always be 0.
8.2.10 Bus Function Extending Register (BSCEHR)
BSCEHR is a 16-bit register that specifies the timing of bus release by the DTC. For more details,
see section 9.4.4, Bus Function Extending Register (BSCEHR).
Rev. 3.00 Oct. 06, 2008 Page 168 of 1080
REJ09B0230-0300