SH7147 Datasheet, PDF (29/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Items
Advanced user
debugger (AUD)
Clock pulse
generator (CPG)
Watchdog timer
(WDT)
Section 1 Overview
Specification
• RAM monitor mode
AUDCK clock: lower than or equal to both 10 MHz and 1/4 of Bφ
Modules connected to the internal or external bus can be read and
written to.
• Branch trace mode
AUD operation frequency: supports CPU core clock ratios of 1, 1/2,
1/4, and 1/8 with a maximum operating frequency of 20 MHz
• Branch address output
• Clock mode: Input clock can be selected from external input or crystal
resonator
• Five types of clocks generated:
⎯ CPU clock: Maximum 80 MHz (T_opr = −40 to +85°C)
⎯ CPU clock: Maximum 64 MHz (T_opr = −40 to +125°C)
⎯ Bus clock: Maximum 40 MHz (T_opr = −40 to +85°C)
⎯ Bus clock: Maximum 32 MHz (T = −40 to +125°C)
opr
⎯ Peripheral clock: Maximum 40 MHz (T_opr = −40 to +85°C)
⎯ Peripheral clock: Maximum 32 MHz (T_opr = −40 to +125°C)
⎯ MTU2 clock: Maximum 40 MHz (T_opr = −40 to +85°C)
⎯ MTU2 clock: Maximum 32 MHz (T_opr = −40 to +125°C)
⎯ MTU2S clock: Maximum 80 MHz (T = −40 to +85°C)
opr
⎯ MTU2S clock: Maximum 64 MHz (T_opr = −40 to +125°C)
• On-chip one-channel watchdog timer
• Interrupt generation is supported.
Rev. 3.00 Oct. 06, 2008 Page 5 of 1080
REJ09B0230-0300