SH7147 Datasheet, PDF (644/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 14 Synchronous Serial Communication Unit
(3) Data Reception
Figure 14.7 shows an example of reception operation, and figure 14.8 shows a flowchart example
of data reception. When receiving data, the synchronous serial communication unit operates as
shown below.
After setting the RE bit to 1 and dummy-reading SSRDR, the synchronous serial communication
unit starts data reception.
In master mode, the synchronous serial communication unit outputs a transfer clock and receives
data. In slave mode, when a low level signal is input to the SCS pin and a transfer clock is input to
the SSCK pin, the synchronous serial communication unit receives data in synchronization with
the transfer clock.
When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is
stored in SSRDR. At this time, if the RIE bit in SSER is set to 1, an RXI interrupt is generated.
The RDRF bit is automatically cleared to 0 by reading SSRDR.
When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in
SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data
reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To
resume the reception, clear the ORER bit to 0.
Rev. 3.00 Oct. 06, 2008 Page 620 of 1080
REJ09B0230-0300