SH7147 Datasheet, PDF (651/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 14 Synchronous Serial Communication Unit
(2) Data Transmission
Figure 14.13 shows an example of transmission operation, and figure 14.14 shows a flowchart
example of data transmission. When transmitting data in clock synchronous communication mode,
the synchronous serial communication unit operates as shown below.
In master mode, the synchronous serial communication unit outputs a transfer clock and data. In
slave mode, when a transfer clock is input to the SSCK pin, the synchronous serial communication
unit outputs data in synchronization with the transfer clock.
Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit in SSSR to 0, and
the SSTDR contents are transferred to SSTRSR. After that, the synchronous serial communication
unit sets the TDRE bit to 1 and starts transmission. At this time, if the TIE bit in SSER is set to 1,
a TXI interrupt is generated.
When 1-frame data has been transferred with TDRE = 0, the SSTDR contents are transferred to
SSTRSR to start the next frame transmission. When the 8th bit of transmit data has been
transferred with TDRE = 1, the TEND bit in SSSR is set to 1 and the state is retained. At this time,
if the TEIE bit is set to 1, a TEI interrupt is generated.
While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit
is cleared to 0 before transmission.
SSCK
SSO
TDRE
TEND
Bit 0
Bit 1
1 frame
Bit 7
Bit 0
Bit 1
1 frame
LSI operation
User operation
TXI interrupt
generated
Data written
to SSTDR
Data written
to SSTDR
TXI interrupt
generated
Figure 14.13 Example of Transmission Operation
(Clock Synchronous Communication Mode)
Bit 7
TEI interrupt
generated
Rev. 3.00 Oct. 06, 2008 Page 627 of 1080
REJ09B0230-0300