SH7147 Datasheet, PDF (255/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
9.5.8 Access to On-Chip FLASH and On-Chip RAM by CPU
Access to the on-chip FLASH for read is synchronized with Iφ clock and is executed in one clock
cycle. For details on programming and erasing, see section 20, Flash Memory.
Access to the on-chip RAM for read/write is synchronized with I φ clock and is executed in one
clock cycle. For details, see section 21, RAM.
9.5.9 Access to On-Chip Peripheral I/O Registers by CPU
Table 9.10 shows the number of cycles required for access to the on-chip peripheral I/O registers
by the CPU.
Table 9.10 Number of Cycles for Access to On-Chip Peripheral I/O Registers
Number of Access Cycles
Write
(3 + n) × Iφ + (1 + m) × Bφ + 2 × Pφ
Read
(3 + n) × Iφ + (1 + m) × Bφ + 2 × Pφ + 2 × Iφ
Notes: 1. When Iφ:Bφ = 8:1, n = 0 to 7.
When Iφ:Bφ = 4:1, n = 0 to 3.
When Bφ:Pφ = 4:1, m = 0 to 3.
When Iφ:Bφ = 3:1, n = 0 to 2.
When Bφ:Pφ = 3:1, m = 0 to 2.
When Iφ:Bφ = 2:1, n = 0 to 1.
When Bφ:Pφ = 2:1, m = 0 to 1.
When Iφ:Bφ = 1:1, n = 0.
When Bφ:Pφ = 1:1, m = 0.
n and m depend on the internal execution state.
2. The clock ratio of MIφ and MPφ does not affect the number of access cycles.
Rev. 3.00 Oct. 06, 2008 Page 231 of 1080
REJ09B0230-0300