SH7147 Datasheet, PDF (1077/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 25 Electrical Characteristics
25.3.14 AUD Timing
Table 25.19 shows AUD timing.
Table 25.19 AUD Timing
Conditions (regular specifications):
V_CC = 4.5 V to 5.5 V, PV_CC = 4.5 V to 5.5 V,
AV_CC = 4.5 V to 5.5 V, AV_refh = 4.5 V to AV_CC,
V_SS = PLLV_SS = AV_SS = AV_refh = 0 V,
T_a = –40°C to +85°C
Conditions (wide-range specifications): V_CC = 3.0 V to 3.6 V, PV_CC = 4.5 V to 5.5 V,
AV_CC = 4.5 V to 5.5 V, AV_refh = 4.5 V to AV_CC,
V_SS = PLLV_SS = AV_SS = AV_refh = 0 V,
T_a = –40°C to +125°C
Item
Symbol Min.
AUDRST pulse width (Branch trace)
AUDRST pulse width (RAM monitor)
AUDMD setup time (Branch trace)
AUDMD setup time (RAM monitor)
Branch trace clock cycle
Branch trace clock duty
Branch trace data delay time
Branch trace data hold time
Branch trace SYNC delay time
Branch trace SYNC hold time
RAM monitor clock cycle
RAM monitor clock low pulse width
RAM monitor output data delay time
RAM monitor output data hold time
RAM monitor input data setup time
RAM monitor input data hold time
RAM monitor SYNC setup time
RAM monitor SYNC hold time
Load conditions: AUDCK (output):
AUDSYNC:
t_AUDRSTW
20
t_AUDRSTW
5
t_AUDMDS
20
t
5
AUDMDS
t
2
BTCYC
t_BTCKW
40
t_BTDD
—
t
50
BTDH
t_BTSD
—
t_BTSH
50
t_RMCYC
100
t_RMCKW
42
t
5
RMDD
t_RMDHD
50
t_RMDS
50
t
50
RMDH
t_RMSS
50
t
50
RMSH
CL = 30 pF
CL = 30 pF
AUDATA3 to AUDATA0: CL = 30 pF
Max.
—
—
—
—
2
60
50
—
50
—
—
—
t -20
RMCYC
—
—
—
—
—
Unit
t_Bcyc
t_RMCYC
t_Bcyc
t
RMCYC
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure
Figure
25.31
Figure
25.32
Figure
25.33
Rev. 3.00 Oct. 06, 2008 Page 1053 of 1080
REJ09B0230-0300