SH7147 Datasheet, PDF (63/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 2 CPU
2.5.3 Arithmetic Operation Instructions
Table 2.12 Arithmetic Operation Instructions
Instruction
ADD Rm,Rn
ADD #imm,Rn
ADDC Rm,Rn
ADDV Rm,Rn
CMP/EQ #imm,R0
Operation
Rn + Rm → Rn
Rn + imm → Rn
Rn + Rm + T → Rn,
Carry → T
Rn + Rm → Rn,
Overflow → T
If R0 = imm, 1 → T
Code
0011nnnnmmmm1100
0111nnnniiiiiiii
0011nnnnmmmm1110
0011nnnnmmmm1111
10001000iiiiiiii
CMP/EQ Rm,Rn
If Rn = Rm, 1 → T
0011nnnnmmmm0000
CMP/HS Rm,Rn
CMP/GE Rm,Rn
CMP/HI Rm,Rn
CMP/GT Rm,Rn
CMP/PZ Rn
If Rn ≥ Rm with
unsigned data, 1 → T
If Rn ≥ Rm with signed
data, 1 → T
If Rn > Rm with
unsigned data, 1 → T
If Rn > Rm with signed
data, 1 → T
If Rn ≥ 0, 1 → T
0011nnnnmmmm0010
0011nnnnmmmm0011
0011nnnnmmmm0110
0011nnnnmmmm0111
0100nnnn00010001
CMP/PL Rn
If Rn > 0, 1 → T
0100nnnn00010101
CMP/STR Rm,Rn
If Rn and Rm have an
equivalent byte, 1 → T
DIV1 Rm,Rn
Single-step division
(Rn/Rm)
DIV0S Rm,Rn
MSB of Rn → Q, MSB
of Rm → M, M^ Q → T
DIV0U
0 → M/Q/T
DMULS.L
Rm,Rn Signed operation of
Rn × Rm → MACH,
MACL 32 × 32 → 64 bits
0010nnnnmmmm1100
0011nnnnmmmm0100
0010nnnnmmmm0111
0000000000011001
0011nnnnmmmm1101
Execution
Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2 to 5*
T Bit
⎯
⎯
Carry
Overflow
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Calculation
result
Calculation
result
0
⎯
Rev. 3.00 Oct. 06, 2008 Page 39 of 1080
REJ09B0230-0300