SH7147 Datasheet, PDF (755/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 17 Controller Area Network (RCAN-ET)
17.6 DTC Interface
The DTC can be activated by the reception of a message in RCAN-ET mailbox 0. When DTC
transfer ends after DTC activation has been set, flags of RXPR0 and RFPR0 are cleared
automatically. An interrupt request due to a receive interrupt from the RCAN-ET cannot be sent to
the CPU in this case. Figure 17.14 shows a DTC transfer flowchart.
DTC initialization
DTC enable register setting
DTC register information setting
: Settings by user
: Processing by hardware
Message reception in RCAN-ET
mailbox 0
DTC activation
No
End of DTC transfer?
Yes
RXPR and RFPR flags clearing
Transfer counter = 0
No
or DISEL = 1?
Yes
Interrupt to CPU
END
Figure 17.14 DTC Transfer Flowchart
Rev. 3.00 Oct. 06, 2008 Page 731 of 1080
REJ09B0230-0300