SH7147 Datasheet, PDF (70/1108 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 2 CPU
2.6 Processing States
The CPU has the five processing states: reset, exception handling, bus release, program execution,
and power-down. Figure 2.4 shows the CPU state transition.
HSTBY = 1,
RES = 0
From any state
when RES = 0
and HSTBY = 1
From any state except
deep software standby mode
when RES = 1, MRES = 0,
and HSTBY = 1
Power-on reset state
RES = 0
Manual reset state
HSTBY = 1,
RES = 0
When internal power-on reset by WDT
or internal manual reset by WDT occurs
RES = 1
Exception
handling state
RES = 1,
MRES = 1
Reset state
Bus request
cleared
Bus release state
Bus request
generated
Bus request
generated
Bus request
cleared
Bus request
generated
Exception
processing
source
occurs
Bus request
cleared
Exception
processing
ends
Program
execution state
SSBY bit = 0
for SLEEP
instruction
SSBY bit = 1 and
STBYMD bit = 1
for SLEEP
instruction
NMI interrupt or IRQ
interrupt occurs
SSBY bit = 1 and
STBYMD bit = 0
for SLEEP
instruction
Sleep mode
Hardware
standby mode
Software
standby mode
Deep software
standby mode
From any state
when HSTBY = 0
Power-down mode
Figure 2.4 Transitions between Processing States
Rev. 3.00 Oct. 06, 2008 Page 46 of 1080
REJ09B0230-0300