SH7265 Datasheet, PDF (959/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
(2) Transmission Using Interrupt-Driven Data Flow Control
Start
Release from reset,
set SSICR configuration bits.
Enable SSIF module,
enable data interrupts,
enable error interrupts.
For n = ( (CHNL + 1) x 2) Loop
Set TRMD, EN, SCKD, SWSD,
MUEN, DEL, PDTA, SDTA, SPDP,
SWSP, SCKP, SWL, DWL, CHNL.
EN = 1,
UIEN = 1, OIEN = 1,
TIE = 1
Wait for interrupt from SSIF.
Data interrupt?
No
Yes
Load data of channel n
Next channel
Use SSIF status register bits
to realign data
after underflow/overflow.
Yes
More data to be sent?
No
Disable SSIF module,
disable data interrupts
disable error interrupts,
enable Idle interrupt.
EN = 0,
UIEN = 0, OIEN = 0,
IIEN = 1, TIE = 0
Wait for idle interrupt
from SSIF module.
End
Figure 19.21 Transmission Using Interrupt-Driven Data Flow Control
Rev. 1.00 Mar. 14, 2008 Page 923 of 1984
REJ09B0351-0100