SH7265 Datasheet, PDF (416/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.3 _{DMA Current Byte Count Register (DMCBCTn)}
DMCBCTn is a register used to specify the number of bytes to be transferred by DMA. The value
in this register is transferred to the working byte-count register when DMA transfer is started and
decremented the number of bytes to be transferred per single data transfer. How much this value is
decremented depends on the transfer data size as follows:
• When the transfer data size is set to 8 bits (SZSEL = 000): -1
• When the transfer data size is set to 16 bits (SZSEL = 001): -2
• When the transfer data size is set to 32 bits (SZSEL = 010): -4
When the value in the working byte count register reaches H'000 0000, DMA transfer ends
(transfer end when the byte count reaches "0"). The corresponding bit of the DMA transfer end
detection register (DMEDET) is set to 1. If the byte count reload function is disabled, the contents
of the working byte count register are returned to this register when the channel for DMA transfer
switches or DMA transfer ends. If the byte count reload function is enabled, the contents of the
DMA reload byte count register (DMRBCTn) are returned to this register when DMA transfer is
completed. This register must be set regardless of whether the reload function is enabled or
disabled.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
CBC[25:16]
Initial value: 0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CBC[15:0]
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Mar. 14, 2008 Page 380 of 1984
REJ09B0351-0100