SH7265 Datasheet, PDF (1590/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 29 AESOP
29.3.7 Event Clear Register (EVCLR)
EVCLR is a 32-bit readable/writable register that clears interrupt source event status. When an
interrupt event is generated, the corresponding bit is automatically set to 1 and continues to be 1
until 0 is written to the bit. Only the bits to which 0 has been written are cleared to 0 and the bits
to which 1 has been written retain the previous value.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
EVC
NPRO
-
-
-
-
-
- EVCDO -
Initial value: 0
0
0
0
0
0
0
1
Unde- Unde- Unde- Unde- Unde- Unde-
fined fined fined fined fined fined
0
Unde-
fined
R/W: R
R
R
R
R
R
R R/W R
R
R
R
R
R R/W R
Bit Bit Name
31 to 9 
Initial
Value
All 0
8
EVCNPRO 1
7 to 2 
Unde-
fined
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Processing Status End Flag Clear
Indicates that encoding processing of the final input data
transferred to the DIN_RAM is complete and also clears
the flag. When encoding processing of the final input
data has been executed and writing to DOUT_RAM is
complete, this bit is set to 1.
0: Clears the flag.
1: Waiting
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Mar. 14, 2008 Page 1554 of 1984
REJ09B0351-0100