SH7265 Datasheet, PDF (845/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Initial
Bit
Bit Name Value R/W
2 to 0 CKS[2:0] 000
R/W
Section 17 Synchronous Serial Communication Unit (SSU)
Description
Transfer Clock Rate Select
Select the transfer clock rate (prescaler division rate)
when an internal clock is selected.
000: Reserved
001: Pφ/4
010: Pφ/8
011: Pφ/16
100: Pφ/32
101: Pφ/64
110: Pφ/128
111: Pφ/256
17.3.4 SS Enable Register (SSER)
SSER enables or disables transmission, reception, and interrupt requests.
Bit: 7
6
5
TE RE
-
Initial value: 0
0
0
R/W: R/W R/W R
4
3
2
1
0
-
TEIE TIE RIE CEIE
0
0
0
0
0
R R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
7
TE
0
R/W
6
RE
0
R/W
5, 4 
All 0
R
3
TEIE
0
R/W
Description
Transmit Enable
When this bit is set to 1, transmission is enabled.
Receive Enable
When this bit is set to 1, reception is enabled.
Reserved
These bits are always read as 0. The write value should
always be 0.
Transmit End Interrupt Enable
When this bit is set to 1, generation of an SSTXI
interrupt request at the end of transmission is enabled.
Rev. 1.00 Mar. 14, 2008 Page 809 of 1984
REJ09B0351-0100