SH7265 Datasheet, PDF (1727/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 34 User Debugging Interface (H-UDI)
34.3 Description of the Boundary Scan TAP Controller
The boundary scan TAP controller has the following registers.
Table 34.2 Register Configuration of the Boundary Scan TAP Controller
Register Name
Bypass register
Instruction register
Boundary scan register
ID register
Abbreviation R/W
BSBPR

BSIR

SDBSR

BSID

Initial Value



H'08057447
Address




Access
Size




34.3.1 Bypass Register (BSBPR)
BSBPR is a 1-bit register that cannot be accessed by the CPU. When BSIR is set to BYPASS
mode, BSBPR is connected between H-UDI pins TDI and TDO. The initial value is undefined.
34.3.2 Instruction Register (BSIR)
BSIR is a 4-bit register and initialized by TRST assertion or in the TAP test-logic-reset state. This
register cannot be accessed by the CPU.
Bit
3 to 0
Initial
Bit Name Value
TI[3:0]
0100
R/W Description
 Test Instruction
The H-UDI instruction is transferred to BSIR as a serial
input from TDI.
For commands, see table 34.3.
Rev. 1.00 Mar. 14, 2008 Page 1691 of 1984
REJ09B0351-0100