SH7265 Datasheet, PDF (1721/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 33 Power-Down Modes
(a) Canceling by an interrupt
When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit (NMIE)
in interrupt control register 0 (C0ICR0, C1ICR0) of the interrupt controller (INTC)) or the falling
edge or rising edge of an IRQ pin (IRQ7 to IRQ0 allocated to PJ3 to PJ0 and PC3 to PC0)
(selected by the IRQn sense select bits (IRQn1S and IRQn0S) in interrupt control register 1
(C0ICR1, C1ICR1) of INTC) is detected, clock oscillation is started after waiting for the power
supply stabilization time.
The clock output phase of the CKIO pin may be unstable immediately after an interrupt is detected
and until deep standby mode is canceled. When deep standby mode is canceled on the falling edge
of the NMI pin, the NMI pin should be high when the CPU enters deep standby mode (when the
clock pulse stops) and should be low when the CPU returns from deep standby mode (when the
clock is initiated after the oscillation settling). When deep standby mode is canceled by the rising
edge of the NMI pin, the NMI pin should be low when the CPU enters deep standby mode (when
the clock pulse stops) and should be high when the CPU returns from deep standby mode (when
the clock is initiated after the oscillation settling). (This is the same with the IRQ pin.)
(b) Canceling by a reset
When the RES pin is driven low, this LSI enters the power-on reset state and deep standby mode
is canceled. Then, the RES pin is driven high and the power-on reset exception handling is
executed. When the RES pin is driven low in clock mode 0, 1, or 3, the internal clock output from
the CKIO is executed.
When the MRES pin is driven low, this LSI enters the power-on reset state and deep standby
mode is canceled. Then, the MRES pin is driven high and the power-on reset exception handling
is executed. When the MRES pin is driven high in clock mode 0, 1, or 3, the internal clock output
from the CKIO is executed.
Keep the RES or MRES pin low until the clock oscillation settles.
(3) Operation after Canceling Deep Standby Mode
After exiting from deep standby mode, the LSI can be booted up either through the external bus or
from the on-chip RAM (for data retention), which can be selected by setting the RAMBOOT bit in
DSCTR. By setting the CS0KEEPE bit, the states of the external bus control pins can be retained
even after cancellation of deep standby mode. Table 33.3 shows the pin states after cancellation of
deep standby mode according to the setting of each bit. Table 33.4 lists the external bus control
pins.
Rev. 1.00 Mar. 14, 2008 Page 1685 of 1984
REJ09B0351-0100