SH7265 Datasheet, PDF (1718/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 33 Power-Down Modes
33.3.7 Deep Standby Mode
(1) Transition to Deep Standby Mode
In single-processor 0 mode where only CPU0 is running, the LSI can enter deep standby mode.
After setting to disable an interrupt to CPU1 and confirming that the SLEEP bit in C1MSR is 1,
when CPU0 executes the SLEEP instruction with the STBY and DEEP bits in STBCR1 set to 1,
the LSI switches from a program execution state to deep standby mode. However, if CPU0
executes the SLEEP instruction when the SLPERE bit in STBCR1 is 1, the LSI does not enter
deep standby mode and a sleep error exception occurs.
In deep standby mode, not only CPU0, CPU1, the clock, and on-chip peripheral modules halt, but
also power supply is turned off except for that supplied to the RTC and the on-chip RAM (for data
retention) area specified by the RRAMKP3 to RRAMKP0 bits in RRAMKP, which can
significantly reduce power consumption. Therefore, data in the registers of the CPU0, CPU1,
cache, and on-chip peripheral modules are not retained. However, the pin state values immediately
before the transition to deep standby mode are retained.
The CPU takes one cycle to finish writing to DSFR, and then executes processing for the next
instruction. However, it actually takes one or more cycles to write. Therefore, execute a SLEEP
instruction after reading DSFR to definitely reflect the values written to DSFR by the CPU in the
SLEEP instruction.
The procedure for switching to deep standby mode is shown below. Figure 33.3 shows its
flowchart.
1. Set the RRAMKP3 to RRAMKP0 bits in RRAMKP for the corresponding on-chip RAM (for
data retention) area that must be retained. Transfer the programs to be retained to the specified
areas of the on-chip RAM (for data retention).
2. When returning from deep standby mode by an interrupt or manual reset, set the corresponding
bits in DSSSR to select the interrupts to cancel deep standby mode. In this case, the detection
mode should be specified appropriately for the input of selected interrupt signals (using the
interrupt control registers 0 and 1 (C0ICR0, C1ICR0, C0ICR1, and C1ICR1) of the INTC). In
the case of recovery from deep standby mode, only rising- or falling-edge detection is
effective. (The LSI cannot recover with the IRQ signals specified for low-level detection or
both-level detection.)
3. Execute read and write accesses to an arbitrary but the same address for each page in the on-
chip RAM (for data retention) area. If this is not executed, data last written may not be written
to the on-chip RAM. If there is any write to the on-chip RAM (for data retention) hereafter,
execute this processing after the last write to the on-chip RAM.
Rev. 1.00 Mar. 14, 2008 Page 1682 of 1984
REJ09B0351-0100