SH7265 Datasheet, PDF (212/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 7 Interrupt Controller (INTC)
7.3.4 Interrupt Control Registers 2 (C0ICR2, C1ICR2)
C0ICR2 and C1ICR2 are 16-bit registers that specify the detection mode for external interrupt
input pins PINT7 to PINT0 individually: low level or high level.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
- PINT7S PINT6S PINT5S PINT4S PINT3S PINT2S PINT1S PINT0S
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15 to 8
Bit Name

Initial
Value
All 0
7
PINT7S 0
6
PINT6S 0
5
PINT5S 0
4
PINT4S 0
3
PINT3S 0
2
PINT2S 0
1
PINT1S 0
0
PINT0S 0
[Legend]
n = 7 to 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W PINT Sense Select
R/W These bits select whether interrupt signals input to pins
R/W ^{PINT7 to PINT0 are detected on a low level or high level.}
R/W ^{0: Interrupt request is detected on low level of PINTn input.}
R/W
1: Interrupt request is detected on high level of PINTn
input.
R/W _{Note: C0ICR2 and C1ICR2 must be the same in each}
R/W
value set in PINT7S to PINT0S.
R/W
Rev. 1.00 Mar. 14, 2008 Page 176 of 1984
REJ09B0351-0100