SH7265 Datasheet, PDF (1204/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
Initial
Bit
Bit Name Value R/W Description
9 to 0 PATn[9:0] All 1
R
nth Error Correction Pattern Indication
Indicates the pattern for the correction of the nth error of
the four errors.
Patterns for which PAT[9:8] = B'11 and patterns for which
all bits of PAT[9:0] are 0 are invalid (and indicate that
generation of an error pattern was not possible or that
there were no errors).
The initial value is H’3FF.
The values of these bits that are set after the 4ECCEND
bit in the 4-symbol ECC control register is set to 1 are
valid. Note that starting to read out the data for the next
sector before reading these bits will destroy the data.
Rev. 1.00 Mar. 14, 2008 Page 1168 of 1984
REJ09B0351-0100