SH7265 Datasheet, PDF (926/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
Channel Register Name
Abbreviation R/W
Initial Value Address
Access
Size
5
Control register 5
Status register 5
SSICR_5
SSISR_5
R/W
R/W*¹
H'00000000
H'02000003
H'FFFEC400
H'FFFEC404
8, 16, 32
8, 16, 32
FIFO control register 5
SSIFCR_5 R/W
H'00000000 H'FFFEC410 8, 16, 32
FIFO status register 5
SSIFSR_5 R/(W)*² H'00000002 H'FFFEC414 8, 16, 32
FIFO data register 5
SSIFDR_5 R/W*³ Undefined
H'FFFEC418 32
Notes: 1. Although bits 26 and 27 in these registers can be read from or written to, bits other than
these are read-only. For details, refer to section 19.3.2, Status Register (SSISR).
2. To bits 1 and 0 in these registers, only 0 can be written to clear the flags. Other bits are
read-only. For details, refer to section 19.3.6, FIFO Status Register (SSIFSR).
3. These registers cannot be written to during reception. For details, refer to section
19.3.7, FIFO Data Register (SSIFDR).
Rev. 1.00 Mar. 14, 2008 Page 890 of 1984
REJ09B0351-0100