SH7265 Datasheet, PDF (1422/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 AT Attachment Packet Interface (ATAPI)
STOP
(IDEIOWR#)
DMARDY
(IDEIORD#)
DCT
DCT
DRP
DCT: Period setting
DRP: Set period from the negation of DMARDY (IDEIORD#) until the STOP (IDEIOWR#) signal is issued
(used during data-in burst)
Note: The DCT and DRP are determined by their respective register settings × enhanced bus clock period.
Figure 27.4 Ultra DMA Timing Register
• Ultra DMA timing register value table
Enhanced Bus Clock
66 MHz
Mode 0
H'010C
Mode 1
H'00C9
Mode 2
H'00A8
Rev. 1.00 Mar. 14, 2008 Page 1386 of 1984
REJ09B0351-0100