SH7265 Datasheet, PDF (1583/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 29 AESOP
29.3 Register Configuration
Table 29.2 lists the AESOP registers. These registers are accessed in 32-bit units. The addresses in
the table represent the lower 17 bits.
Table 29.2 AESOP Register Configuration
Register Name
Abbreviation R/W
Software reset register
SWRSR
R/W
Encoding processing initialization
RPRSR
R/W
register
DMA control register
DMACR
R/W
DMA transfer register for DIN_RAM DMADI
W
buffer write
DMA transfer register for DOUT_RAM DMADO
R
buffer read
Reserved


Reserved


Event mask register
EVMSR
R/W
Reserved


Event clear register
EVCLR
R/W
Setting-predetermined register 1
MBOTR
R/W
Setting-predetermined register 2
BACCR
R/W
Setting-predetermined register 3
ACESR
R/W
Audio processing information setting ADIFR
R/W
register
Setting-predetermined register 4
TBRSR
R/W
Header setting register
HEADR
R/W
ADTS format header information
ADTSR
R/W
setting register
Setting-predetermined register 5
MSS1R
R/W
Setting-predetermined register 6
MSS2R
R/W
Setting-predetermined register 7
QLMDR
R/W
Setting-predetermined register 8
QCHAR
R/W
Setting-predetermined register 9
QGGAR
R/W
Initial Value Address
Access
Size
H'00000001 H'FFA10000 32
H'00000000 H'FFA10004 32
H'00000000 H'FFA10008 32
Undefined H'FFA1000C 32
Undefined H'FFA10010 32

H'FFA10014 32

H'FFA10018 32
H'00000000 H'FFA1001C 32

H'FFA10020 32
H'00000101 H'FFA10024 32
H'00000000 H'FFA10028 32
H'00000000 H'FFA1002C 32
H'00000000 H'FFA10030 32
H'00000004 H'FFA10034 32
H'00000000 H'FFA10038 32
H'00000000 H'FFA1003C 32
H'00000000 H'FFA10040 32
H'00000000 H'FFA10044 32
H'00000000 H'FFA10048 32
H'00000000 H'FFA1004C 32
H'00000000 H'FFA10050 32
H'00000000 H'FFA10054 32
Rev. 1.00 Mar. 14, 2008 Page 1547 of 1984
REJ09B0351-0100