SH7265 Datasheet, PDF (1495/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 28 2D Graphics Engine (2DG)
28.4 Operation
SA buffer (Double-buffer structure)
(16 bits × 64 words × 2 planes)
SB buffer (Double-buffer structure)
(16 bits × 64 words × 2 planes)
Conversion of pixel format (16 → 19)
α → 4 bits + RGB → 555 (15 bits)
Conversion of pixel format (16 → 19)
α → 4 bits + RGB → 555 (15 bits)
DC buffer
(Double-buffer structure)
(16 bits × 256 words
× 2 planes)
Target color
determination
Chromakey processing
Replacement color
(Register)
Logical operations
(Three types)
Color gradation
processing
α
RGB
2-to-1 selection
4-to-1 selection
α blending
Pixel format conversion (19 → 16)
Pre-filtering
(2-point moving average)
2-to-1 selection
Resizing block _{Horizontal resizing}
Vertical resizing
Figure 28.2 Block Diagram of the Blitter
Rev. 1.00 Mar. 14, 2008 Page 1459 of 1984
REJ09B0351-0100