SH7265 Datasheet, PDF (1697/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 33 Power-Down Modes
Initial
Bit Bit Name Value R/W Description
7 to 4 
All 1 R
Reserved
These bits are always read as 1. The write value should
always be 1.
3
RAMWE3 1
R/W RAM Write Enable 3 (page 3 of high-speed on-chip RAM0*)
0: Write to page 3 is disabled
1: Write to page 3 is enabled
2
RAMWE2 1
R/W RAM Write Enable 2 (page 2 of high-speed on-chip RAM0*)
0: Write to page 2 is disabled
1: Write to page 2 is enabled
1
RAMWE1 1
R/W RAM Write Enable 1 (page 1 of high-speed on-chip RAM0*)
0: Write to page 1 is disabled
1: Write to page 1 is enabled
0
RAMWE0 1
R/W RAM Write Enable 0 (page 0 of high-speed on-chip RAM0*)
0: Write to page 0 is disabled
1: Write to page 0 is enabled
Note: * For the addresses of each page, see section 32, On-Chip RAM.
Rev. 1.00 Mar. 14, 2008 Page 1661 of 1984
REJ09B0351-0100