SH7265 Datasheet, PDF (1607/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 29 AESOP
(1) When a Timer Interrupt Is Not Used
Figure 29.10 shows a flowchart of procedures when a timer interrupt is not used in processing
status end interrupt processing. For the number of data output DMA transfers from the AESOP,
specify 4-Kbyte (32-bit access × 1024-time transfers) except when the number of times of forcible
transfers is set.
After input PCM data of the final frame has been transferred, once clear the interrupt source
(EVCLR). After the interrupt source is cleared, set the ENVPRO bit in EVMSR to enable AESOP
interrupts. This allows an AESOP interrupt to be generated when encoding processing of the final
frame PCM data and writing data to the DOUT_RAM are complete.
After an AESOP interrupt is confirmed, disable interrupt sources by clearing the EVNPRO bit in
EVMSR to clear the interrupt source. After interrupts are disabled, set to suspend DMA transfer
by the DMAC from DOUT_RAM, and then clear the interrupt source (EVCLR).
After 10 cycles of the AESOP clock, the interrupt source (EVCLR) is updated. Then read the
interrupt source value (EVCLR).
If the EVCDO bit in EVCLR is 0, specify forcible transfer setting to transfer data less than 4
Kbytes that was stored in the DOUT_RAM because there is no DOUT_RAM data being
transferred.
On the other hand, if the EVCDO bit in EVCLR is 1, restart DMA transfer by the DMAC because
there is DOUT_RAM data being transferred. After DMA transfer was restarted, a DMA transfer
end interrupt is generated. When the interrupt is generated, specify forcible transfer setting to
transfer data less than 4 Kbytes that was stored in the DOUT_RAM.
For forcible transfer, set the PUSH bit in SDFOR. At this time, read SDBTR to confirm the
amount of DOUT_RAM data to be forcibly transferred. Then, compute the number of times of
transfers from the amount of read data bytes, and set DMA transfer with the DMAC. After data
has been transferred, a DMA end interrupt is generated and processing ends. At this time, the
PUSH bit in SDFOR enters a wait state, which indicates the end of forcible transfer.
Rev. 1.00 Mar. 14, 2008 Page 1571 of 1984
REJ09B0351-0100