SH7265 Datasheet, PDF (213/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 7 Interrupt Controller (INTC)
7.3.5 IRQ Interrupt Request Registers (C0IRQRR, C1IRQRR)
C0IRQRR and C1IRQRR are 16-bit registers that indicate interrupt requests from external
interrupt input pins IRQ7 to IRQ0. If edge detection is set for the IRQ7 to IRQ0 interrupts, the
retained interrupt requests can be cancelled by reading 1 from the IRQ7F to IRQ0F bits and then
writing 0 to these bits. However, this register is enabled only when C0IRQER and C1IRQER
accept an interrupt request input. When an interrupt request input is disabled, this register always
becomes 0.
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
- IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15 to 8
Initial
Bit Name Value R/W

All 0 R
7
IRQ7F 0
R/W
6
IRQ6F 0
R/W
5
IRQ5F 0
R/W
4
IRQ4F 0
R/W
3
IRQ3F 0
R/W
2
IRQ2F 0
R/W
1
IRQ1F 0
R/W
0
IRQ0F 0
R/W
[Legend]
n = 7 to 0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
IRQ Interrupt Request
These bits indicate the status of the IRQ7 to IRQ0 interrupt
requests.
Level detection:
0: IRQn interrupt request has not occurred.
[Clearing condition]
• IRQn input is high
1: IRQn interrupt request has occurred.
[Setting condition]
• IRQn input is low
Edge detection:
0: IRQn interrupt request is not detected.
[Clearing condition]
• Cleared by reading 1 from IRQnF, and then writing 0 to
IRQnF
• Cleared by executing IRQn interrupt exception handling
1: IRQn interrupt request is detected.
[Setting condition]
• Edge corresponding to IRQn1S or IRQn0S of C0ICR1
or C1ICR1 has occurred at IRQn pin
Rev. 1.00 Mar. 14, 2008 Page 177 of 1984
REJ09B0351-0100