SH7265 Datasheet, PDF (1226/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
24.6 DMA Transfer Specifications
The FLCTL can request DMA transfers separately to the data area FLDTFIFO and control code
area FLECFIFO. Table 24.6 summarizes DMA transfer enable or disable states in each access
mode.
Table 24.6 DMA Transfer Specifications
FLDTFIFO
FLECFIFO
Sector Access Mode
DMA transfer enabled
DMA transfer enabled
Command Access Mode
DMA transfer enabled
DMA transfer disabled
For details on DMAC settings, see section 11, Direct Memory Access Controller (DMAC).
Rev. 1.00 Mar. 14, 2008 Page 1190 of 1984
REJ09B0351-0100