SH7265 Datasheet, PDF (1196/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
Initial
Bit
Bit Name Value R/W Description
4
STERINTE 0
R/W Interrupt Enable at Status Error
Enables or disables an interrupt request to the CPU
when a status error has occurred.
0: Disables the interrupt request to the CPU by a status
error
1: Enables the interrupt request to the CPU by a status
error
3
RBERINTE 0
RW Interrupt Enable at R/B Timeout Error
Enables or disables an interrupt request to the CPU
when a timeout error has occurred.
0: Disables the interrupt request to the CPU by an R/B
timeout error
1: Enables the interrupt request to the CPU by an R/B
timeout error
2
TEINTE 0
R/W Transfer End Interrupt Enable
Enables or disables an interrupt request to the CPU
when a transfer has been ended (TREND bit in
FLTRCR).
0: Disables the transfer end interrupt request to the
CPU
1: Enables the transfer end interrupt request to the CPU
1
TRINTE1 0
R/W FLECFIFO Transfer Request Enable to CPU
Enables or disables an interrupt request to the CPU by
a transfer request issued from FLECFIFO.
0: Disables an interrupt request to the CPU by a
transfer request from FLECFIFO.
1: Enables an interrupt request to the CPU by a transfer
request from FLECFIFO.
When the DMA transfer is enabled, this bit should be
cleared to 0.
Rev. 1.00 Mar. 14, 2008 Page 1160 of 1984
REJ09B0351-0100