SH7265 Datasheet, PDF (345/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Bus State Controller (BSC)
CKIO
Ts Tw1 ^... Twn Tend Tpw1 Tpw2 ^... Tpwn Tend Tn1 Tn2 ^... Tnm
(Trd)
(Trd)
Bus access (first time)
Bus access
(second and subsequent times)
Read cycle wait
Page read cycle wait
A25 to A0
CSn
RD_WR
RD
A0
CS assert wait
A1
CS delay cycle during read (end only)
RD assert wait
RD assert wait*
WEn
D31 to D0
DACTn
Note: * RD assert wait operation during the second and subsequent bus accesses differs depending on the page
read access mode setting value.
Figure 10.4 Basic Bus Timing (Page Read Operation in Byte-Write Strobe Mode)
Rev. 1.00 Mar. 14, 2008 Page 309 of 1984
REJ09B0351-0100