SH7265 Datasheet, PDF (10/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 3 Floating-Point Unit (FPU)................................................................... 93
3.1 Features............................................................................................................................... 93
3.2 Data Formats....................................................................................................................... 94
3.2.1 Floating-Point Format......................................................................................... 94
3.2.2 Non-Numbers (NaN) .......................................................................................... 97
3.2.3 Denormalized Numbers ...................................................................................... 98
3.3 Register Descriptions.......................................................................................................... 99
3.3.1 Floating-Point Registers ..................................................................................... 99
3.3.2 Floating-Point Status/Control Register (FPSCR) ............................................. 100
3.3.3 Floating-Point Communication Register (FPUL) ............................................. 102
3.4 Rounding .......................................................................................................................... 103
3.5 FPU Exceptions ................................................................................................................ 104
3.5.1 FPU Exception Sources .................................................................................... 104
3.5.2 FPU Exception Handling .................................................................................. 104
Section 4 Multi-Core Processor......................................................................... 107
4.1 Features............................................................................................................................. 107
4.2 Register Descriptions........................................................................................................ 108
4.2.1 CPU ID Register (CPUIDR)............................................................................. 109
4.2.2 Semaphore Registers 0 to31 (SEMR0 to SEMR31) ......................................... 110
4.3 Operation .......................................................................................................................... 111
4.3.1 Initializing This LSI.......................................................................................... 111
4.3.2 Exclusive Control for CPUs ............................................................................. 112
Section 5 Clock Pulse Generator (CPG) ........................................................... 115
5.1 Features............................................................................................................................. 115
5.2 Input/Output Pins.............................................................................................................. 119
5.3 Clock Operating Modes .................................................................................................... 120
5.4 Register Descriptions........................................................................................................ 125
5.4.1 Frequency Control Registers 0 and 1 (FRQCR0 and FRQCR1) ...................... 125
5.5 Changing the Frequency ................................................................................................... 130
5.5.1 Changing the Multiplication Rate ..................................................................... 130
5.5.2 Changing the Division Ratio............................................................................. 132
5.5.3 Notes on Changing the Multiplication Rate and Division Ratio....................... 133
5.6 Notes on Board Design ..................................................................................................... 134
5.6.1 Note on Inputting the External Clock ............................................................... 134
5.6.2 Note on Using a Crystal Resonator................................................................... 134
5.6.3 Note on the Resonator....................................................................................... 135
5.6.4 Note on Using a PLL Oscillation Circuit.......................................................... 135
Rev. 1.00 Mar. 14, 2008 Page x of xxxvi