SH7265 Datasheet, PDF (1597/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 29 AESOP
29.3.21 Stream Data Forcible Transfer Register (SDFOR)
SDFOR is a 32-bit readable/writable register that forcibly transfers data stored in the
DOUT_RAM buffer.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- PUSH
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
Bit Bit Name
31 to 1 
0
PUSH
Initial
Value R/W
All 0 R
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
DOUT_RAM Stored Data Forcible Transfer Setting
When this bit is set to 1, data stored in the DOUT_RAM is
forcibly transferred. When the forcible transfer ends
normally, this bit is automatically cleared to 0.
0: Waiting
1: Forcible transfer
Rev. 1.00 Mar. 14, 2008 Page 1561 of 1984
REJ09B0351-0100